High yield fabrication process for 3D-stacked ultra-thin chip packages using photo-definable polyimide and symmetry in packages

Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach. At first thinned dies are embedded in a polyimide interposer with a fine-pitch metal fan-out resulting Ultra-Thin Chip Packages (UTCP), next these UTCPs are stacked by lamination. Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by introduction of an additional layer of interposer which makes it flat at the chip edge and thus the whole packages is named as “Flat-UTCP”. In addition to that, randomness in non-functional package positions per panel reduces the overall yield of the whole process up to certain extent. A detailed analysis on these two issues to improve the process yield is presented in this paper. 3D-stacked memory module composed of 4 EEPROM dies was processed and tested to demonstrate this new concept for enhancing the fabrication yield

An approach to produce a stack of photo definable polyimide based flat UTCPs

Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology which has a broad range of industrial and medical electronic applications. This can be achieved by laminating multiple layers of spin-on polyimide based ultrathin chip packages (UTCPs) with fine pitch through hole interconnects

3D stacking of ultrathin chip packages: an innovative packaging and interconnection technology

In order to increase the functionality of electronic devices, while reducing the overall size and weight of the electronic chip packages, electronic chip packages can be combined into a 3D assembly. In this field we present a technology for stacking of multiple chip packages, resulting in a total volume almost equal to that of a single bare die. The technology is based on batch-processed ultra-thin chip packages (UTCPs) with a fine pitch metal fan-out. Package-on-package (PoP) technology enables stacking of UTCPs by vacuum lamination, followed by through hole interconnection technology for making contacts to the metal fan-out of the embedded UTCPs within the stack. The individual chip packages can be tested before stacking

High-yield embedding of 30µm thin chips in a flexible PCB using a photopatternable polyimide based ultra-thin chip package (UTCP)

Thinning down ICs is a well-known approach to reduce the volume of chip packages. In this work ICs are thinned down to 30um, followed by a package procedure in polyimide with copper fan out, which allows their embedding in adhesives used for laminating flexible printed circuit boards (PCBs). In this way the chip does not consume PCB area, hence other circuit components can be assembled on top or at the bottom of the chip, enabling extreme circuit miniaturization. Furthermore, our ultra-thin chip package (UTCP) is highly flexible, enabling flexible electronic circuits without large rigid chip packages. Spin-on photo-definable polyimide precursors are used to build an interposer which can be embedded later in the flexible PCB. The chip is fixed in between three polyimide layers using BCB as adhesive. The central polyimide layer forms a cavity for the chip, the top layer of polyimide is exposed and developed to fabricate vias contacting the chip. An 8um thick copper layer is deposited and patterned using lithography and etching to form the fan-out, essential to match the fine IC pitch to the larger PCB pitch. The final chip package is about 75um thick, and is easily embedded using only small adaptations of the standard flexible PCB fabrication process. Last year, both the UTCP concept and the embedding in a flexible PCB were optimized in order to obtain a very high yield. Three types of chips were UTCP-packaged and embedded in a flexible PCB: two types of microcontrollers (MSP430F1611 and a proprietary digital signal processor) and an RF-chip. The yield of the tested UTCPs ranges in between 65% (proprietary IC) and 85% (MSP430F1611). The performance of the RF-chips can only be tested after embedding in a flexible substrate. Although the testing is still ongoing, 95% of the embedded UTCPs are fully functional after embedding

Photo-definable polyimide-based flat UTCP technology for 3D-stacking application

A 3D-packaging technology is developed which focuses on stacking and interconnecting multiple thinned dies, in order to obtain a functional multi-chip package within the volume of single standard-thickness die. This can be achieved by laminating multiple layers of spin-on polyimide based ultrathin chip packages (UTCPs). The use of thin-film technology allows realizing multiple fan-outs with a fine pitch, interconnected with through-hole vias. This novel 3D integration technology has a broad range of industrial and medical electronic applications

Module miniaturization by ultra thin package stacking

The scope of the European project TIPS (Thin Interconnected Package Stacks) is the fabrication of ultra thin packages for electronic components and the subsequent stacking and interconnection of those packages to form highly compact modules. In the first part of this paper approaches to fabricate ultra thin 10 × 10 mm packages by embedding technologies for chips into printed circuit board environments will be discussed. One technology uses commercial flexible printed circuit board substrates (polyimide sandwiched in Cu layers) and respective fabrication processes. After initial patterning of the Cu the chips are die bonded to the flex substrates and subsequently laminated into build up layers. Electrical contact between the chip and a fan out routing on the outer layer of the package are made by micro via formation, electroplating and wet chemical structuring of the metal layers. The thickness of the embedded components is constricted to 50 μm in order to constrain the package thicknesses to a maximum of 100 μm with this approach. The alternative approach, the ultra thin chip package (UTCP) technology, aims at package thicknesses around 60 μm. In this case 20 μm thick chips are die-bonded to thin polyimide layer. A photo-definable polyimide is then applied over the assembled chips by spin-on technique. Contact pads are opened by exposure and development of the polyimide, followed by metal sputtering, electroplating and etching. In this approach the thickness of embedded components is typically 20-30 μm and final package thickness is in the range of 60 μm. In both approaches the packages are fabricated as batches consisting of 150 × 150 mm sheets of flex substrates. Stacking of individual packages can be performed in an automated package by package placement process using a frame as alignment tool and typical flexible printed circuit boards adhesives. In this way only known-good-packages are stacked in o- - rder to minimize yield loss. However, a more straight forward process is stacking of the packages using fabrication batches and established multilayer printed circuit board technologies. The disadvantage is the potential yield loss if one of the packages in a stacked layer is faulty. For either type of stacking process the individual stacks have to be milled out of the stack fabrication batch. Development issues, design considerations and results of first fabrication runs will be presented and discussed

3D-stacking of UTCPs as a module miniaturization technology

3D-stacking of Ultra Thin Chip Packages (UTCP’s) – one of the emerging technologies in the field of high density integration - is presented here. This technology is developed to increase the functionality of the electronic devices and to raise the comfort zone by reducing the overall size and weight of the package. This has a bright future in the area of mobile communication, medical equipments like hearing aids, implants, patient monitoring. This paper describes an approach to produce miniaturized modular packages by using Ultrathin Chip Package Technology, stacking and through-hole (TH) interconnection technology. UTCP technology is a board level packaging concept, based on embedding of ultra-thin chips (~20 µm) within two 20 µm thick spin-on polyimide layers resulting in a thin flexible chip package of thickness ~50 µm. Stacking of the 4 layers of UTCPs by using 25 µm thick layers of adhesive films and vacuum lamination processes results in stacked UTCP modules of total thickness ~300 µm. The connection to the different layers of the UTCPs is realized by drilling THs on the outer contact pads on the stacked packages, followed by metallization of these THs by Cu electroless deposition, electroplating and finally metal structuring. After processing and testing, the stacks can be easily mounted within functional demonstrators (e.g, Hearing Aid device, etc) replacing single silicon die of almost same size, but with 4 times output